
2010-2012 Microchip Technology Inc.
DS39977F-page 169
PIC18F66K80 FAMILY
10.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack.
If a fast return from interrupt is not used (see
), the user
may need to save the WREG, STATUS and BSR regis-
ters on entry to the Interrupt Service Routine (ISR).
Depending on the user’s application, other registers
also may need to be saved.
and BSR registers during an Interrupt Service Routine.
EXAMPLE 10-1:
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
TABLE 10-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
PIR1
PSPIP
ADIF
RC1IF
TX1IF
SSPIF
TMR1GIF
TMR2IF
TMR1IF
PIR2
OSCFIF
—
BCLIF
HLVDIF
TMR3IF
TMR3GIF
PIR3
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
—
PIR4
TMR4IF
EEIF
CMP2IF
CMP1IF
—
CCP5IF
CCP4IF
CCP3IF
PIR5
IRXIF
WAKIF
ERRIF
TXB2IF
TXB1IF
TXB0IF
RXB1IF
RXB0IF
PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSPIE
TMR1GIE
TMR2IE
TMR1IE
PIE2
OSCFIE
—
BCLIE
HLVDIE
TMR3IE
TMR3GIE
PIE3
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
—
PIE4
TMR4IE
EEIE
CCP2IE
CMP1IE
—
CCP5IE
CCP4IE
CCP3IE
PIE5
IRXIE
WAKIE
ERRIE
TXB2IE
TXB1IE
TXB0IE
RXB1IE
RXB0IE
IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSPIP
TMR1GIP
TMR2IP
TMR1IP
IPR2
OSCFIP
—
BCLIP
HLVDIP
TMR3IP
TMR3GIP
IPR3
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
—
IPR4
TMR4IP
EEIP
CMP2IP
CMP1IP
—
CCP5IP
CCP4IP
CCP3IP
IPR5
IRXIP
WAKIP
ERRIP
TXB2IP
TXB1IP
TXB0IP
RXB1IP
RXB0IP
RCON
IPEN
SBOREN
CM
RI
TO
PD
POR
BOR
Legend:
Shaded cells are not used by the interrupts.
MOVWF
W_TEMP
; W_TEMP is in virtual bank
MOVFF
STATUS, STATUS_TEMP
; STATUS_TEMP located anywhere
MOVFF
BSR, BSR_TEMP
; BSR_TMEP located anywhere
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
; Restore BSR
MOVF
W_TEMP, W
; Restore WREG
MOVFF
STATUS_TEMP, STATUS
; Restore STATUS